[asahi kasei] [AK4543] 1999/01 - 1 - analog section input multiplexer adc dac control signals line_in sync data_out sdata_in bit_clock reset# cd aux video mic2 mic1 phone pc_beep line_out true_line_level mono_out ac'97 registers and control logic ac link interface power management clock generator 3d stereo enhancement output mixer volume and mute control volume and mute control digital section multiple codec support codec id# voltage reference eapd sel_cmos 18bit 18bit general description the AK4543 is a 18bit high performance codec compliant with audio codec 97 rev 2.1 requirements. the ac link serial interface allows the AK4543 to be used with digital controllers as well as custom logic accelerators to meet full pc98 and pc99 requirements for a pci audio solution. the AK4543 provides two pairs of stereo outputs with independent volume controls along with a mono output, multiple stereo and mono inputs, are combined to create flexible mixing, gain and mute functions to provide a complete integrated audio solution for pcs. the AK4543 can function as a primary ac97 or secondary codec depending on the codec id configuration(multiple codec extension), making the AK4543 suitable for the docking station application and multiple codec applications such as 4 speaker output or 6 speaker output. sampling at 48khz, the AK4543 provides excellent audio performance, meeting or exceeding all standard requirements. it offers low power consumption, and flexible power-down modes for use in laptops, desktop pcs, and aftermarket add-in boards. like the earlier pin-compatible ak4540 and ak4542, the AK4543 is available in a compact 48-lead lqfp package. the AK4543 is a pin compatible upgrade for the ak4540 and ak4542, some software changes will be required to experience the extra functions ot the AK4543. features ac97 rev. 2.1 compliant 18bit resolution a/d and d/a exceeds a pc98/99 performance categories: a/d 90dba snr d/a 90dba snr d/a + mixer 89dba snr a-a 95ba snr analog inputs: 4 stereo inputs: line, cd, video, aux speakerphone and pc beep inputs 2 independent mic inputs direct pc_beep pass through for lower system costs analog output: stereo line output with volume control true line level with volume control mono output with volume control 3d stereo enhancement multiple codec capability the AK4543 can work as a primary or secondary. eapd(external amplifier powerdown) support power supplies: analog 5.0v, digital 3.3v or 5.0v low power consumption 200mw(analog:5v/digital:3.3v) at full operation 48 pin lqfp package ac97 ? rev 2.1 multimedia audio codec AK4543 * akm assumes no res p onsibilit y for the usa g e be y ond the conditions in this data sheet.
[asahi kasei] [AK4543] 1999/01 - 2 - 42 41 40 39 38 37 mono_out avdd2 nc lnlvl_out_l lnlvl_out_r avss2 test2 43 test3 44 codec id0# 45 codec id1# 46 47 eapd 1 48 sel_cmos line_out_l nc nc 3dcap vradda afiltr afiltl nc vref avss1 avdd1 line_out_r dvdd1 2 xtl_in 3 xtl_out 4 dvss1 5 sdata_out 6 bit_clk 7 sdata_in 8 dvdd2 9 sync 10 reset# 11 12 dvss2 pc_beep 19 20 21 22 23 24 line_in_r line_in_l mic2 mic1 cd_r cd_gnd 18 cd_l 17 video_r 16 video_l 15 aux_r 14 aux_l 13 phone 36 35 25 26 27 28 29 30 31 32 33 34
[asahi kasei] [AK4543] 1999/01 - 3 - pin/function no. signal name i/o description 1 dvdd1 - digital power supply; 3.3v or 5.0v(dvdd1 = dvdd2) 0.1uf + 4.7uf capacitors should be connected to digital ground. 2 xtl_in (mclki) i 24.576mhz(512fs) crystal is normally connected. if a crystal is not connected, an external clock can be used. 3 xtl_out(open) o 24. 576mhz(512fs) crystal. if an external clock is used, this pin should be open. 4 dvss1 - digital ground; 0v this pin should be directly connected to dvss2 on board. 5 sdata_out i serial 256-bit ac?97 data stream from digital controller 6 bit_clk i/o 12.288mhz(256fs) serial data clock output when primary codec(codec id=00). input when secondary codec(codec id=01, 10, 11). 7 dvss2 - digital ground; 0v this pin should be directly connected to dvss1 on board. 8 sdata_in o serial 256-bit ac?97 data stream to digital controller 9 dvdd2 - digital power supply; 3.3v or 5.0v(dvdd1 = dvdd2) 0.1uf + 4.7uf capacitors should be connected to digital ground. 10 sync i ac?97 sync clock, 48khz(1fs) fixed rate sampling rate 11 reset# i ac?97 master hardware reset 12 pc_beep i pc speaker beep pass through 13 phone i from telephony subsystem speakerphone 14 aux_l i aux left channel 15 aux_r i aux right channel 16 video_l i video audio left channel 17 video_r i video audio right channel 18 cd_l i cd audio left channel 19 cd_gnd i cd audio analog ground; 0v cd_gnd or analog ground should be connected. 20 cd_r i cd audio right channel 21 mic1 i desktop microphone input 22 mic2 i second microphone input 23 line_in_l i line in left channel 24 line_in_r i line in right channel 25 avdd1 - analog power supply; 5.0v(avdd1=avdd2) 0.1uf + 4.7uf capacitors should be connected to avss1(analog ground). 26 avss1 - analog ground; 0v 27 vref o reference voltage output; 0.1 m f +4.7 m f capacitors should be connected to avss1(analog ground). 28 nc - no connection 29 afiltl o anti-aliasing filter cap; connected to analog ground with 1nf capacitor. 30 afiltr o anti-aliasing filter cap; connected to analog ground with 1nf capacitor. 31 vradda o vref for adc and dac; 0.1 m f capacitor should be connected to analog ground. 32 3dcap o 3d enhancement cap; 27nf capacitor should be connected to analog ground. 33 nc - no connection 34 nc - no connection 35 line_out_l o line out left channel 36 line_out_r o line out right channel 37 mono_out o to telephony subsystem speakerphone 38 avdd2 - analog power supply; 5.0v(avdd1=avdd2) 0.1uf capacitor should be connected to avss2(analog ground). 39 lnlvl_out_l o true line level out left channel 40 nc - no connection 41 lnlvl_out_r o true line level out right channel 42 avss2 - analog ground; 0v 43 test2 i test pin (this pin should be open for normal operation) 44 test3 i test pin (this pin should be open for normal operation) 45 codec id0# i codec id configuration(id select input for multiple codec extension) see page20. 46 codec id1# i codec id configuration(id select input for multiple codec extension) see page20. 47 eapd o external amplifier powerdown see page 20.
[asahi kasei] [AK4543] 1999/01 - 4 - 48 sel_cmos i cmos/ttl selection for digital input levels see page 28. cmos: leave open for 3.3v supply. ttl : tie to gnd for 5v supply. absolute maximum rating avss1, avss2, dvss1, dvss2 =0v (note 1) parameter symbol min max units power supplies analog(avdd1 & avdd2) digital(dvdd1 & dvdd2) va vd -0.3 -0.3 6.0 6.0 v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 va+0.3 v digital input voltage vind -0.3 vd+0.3 v ambient temperature ta -10 70 c storage temperature ta -65 150 c note 1: all voltages with respect to ground . agnd(avss1, avss2) and dgnd(dvss1, dvss2) must be the same voltage. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating condition agnd, dgnd=0v (note 1) parameter symbol min typ max units power supplies AK4543 analog digital va vd 4.75 3.135 5.0 3.3 or 5.0 5.25 5.25 v v note 1 : all voltages with respect to ground.
[asahi kasei] [AK4543] 1999/01 - 5 - AK4543 analog characteristics ta=25 c,avdd=5.0v 5%, dvdd=3.3v 5% or 5v 5%, fs=48khz, signal frequency =1khz all volume setting for adc/dac performance measurement is 0db. parameter min typ max units audio-adc resolution 18 bits s/n (a weighted) 85 90 db s/(n+d) (-1db analog input) 70 77 dbfs inter channel isolation 70 77 db inter channel gain mismatch 0.5 db full scale input voltage 0.88 1.0 1.12 vrms power supply rejection 50 db audio dac: measured at aoutl/aoutr via mixer path resolution 18 bits s/n (a weighted) : mixer+dac measured at aout 84 89 db s/(n+d) (-1db digital input) 75 83 dbfs inter channel isolation 70 80 db inter channel gain mismatch 1.0 db full scale output voltage 0.83 0.95 1.07 vrms total out-of-band noise (28.8khz - 100khz) -70 db power supply rejection 50 db mic amplifier / mux gain : 20db is selected 18 20 22 db master volume (mono, stereo, true line level out) : 1.5db x 32 step step size -1.5 db attenuation control range -46.5 0 db load resistance 10 k w pc beep : 3db x 16 step step size -3.0 db attenuation control range -45 0 db analog mixer : 1.5db x 32 step step size -1.5 db gain control range -34.5 +12 db record gain : 1.5db x 16 step step size +1.5 db gain control range 0 +22.5 db mixer input voltage (except for mic) 1.0 vrms input voltage mic : gain = 0db mic : gain = 20db 1.0 0.1 vrms vrms s/n(a weighed) : 0db setting, 1 path is selected at mixer cd to aout: other analog input to aout 85 95 95 db db input impedance (input gain=0db,rec_mute=off) pc_beep only others(phone, line, cd, aux, video) input impedance (mic1 and mic2) (10) (10) (10) 80 40 22 k w k w k w power supplies analog power supply current(avdd1 & avdd2) all on mode(all pr_bits are 0) cold reset status(reset#=l, vref is on) all off mode(all pr_bits are 1) 36 2.5 0 54 5 0.2 ma ma ma digital power supply current(dvdd1 & dvdd2) all on mode(all pr_bits are 0) at dvdd=5v all on mode(all pr_bits are 0) at dvdd=3.3v all off mode(all pr_bits are 1) 13 6.6 0 20 10 0.2 ma ma ma
[asahi kasei] [AK4543] 1999/01 - 6 - filter characteristics ta=25 c,avdd=5.0v 5%, dvdd=3.3v 5% or 5v 5% , fs=48khz(fixed) parameter min typ max units adc digital filter (decimation lpf) passband ( 0.2db) 0 19.2 khz stopband 28.8 khz stopband attenuation 70 db group delay 0.5 ms adc digital filter (hpf) frequency response; -3db -0.5db -0.1db 7.5 21 49 hz dac digital filter passband ( 0.2db) 0 19.2 khz stopband 28.8 khz group delay 0.5 ms stopband rejection 70 db dac post filter passband frequency response (0 - 19.2khz) 0.1 db AK4543 dc characteristics ta=-10 ~ 70 c, vd=5v 5%(sel_cmos=l) or 3.3v 5%(sel_cmos=h: open), va=5v 5%, 50pf external load parameter symbol min typ max units ?h? level input voltage xtal_in reset#, sync, sdata_out, bit_clk at sel_coms=l(gnd) at sel_coms=h(open) id0#, id1#, sel_cmos(pull up) vih 0.7xvd 2.2 0.7xvd 0.8xvd -- v v v v ?l? level input voltage xtal_in reset#, sync, sdata_out, bit_clk at sel_coms=l(gnd) at sel_coms=h(open) id0#, id1#, sel_cmos(pull up) vil - - 0.3xvd 0.8 0.3xvd 0.2xvd v v v v ?h? level output voltage iout= -1ma voh vd-0.55 - - v ?l? level output voltage iout= 1ma vol - - 0.55 v input leakage current(exclude pull up pins) iin - - 10 m a pull up resistance rup 50 100 200 k w
[asahi kasei] [AK4543] 1999/01 - 7 - switching characteristics ta=25 c, avdd=5.0v 5%, dvdd=3.3v 5% or 5v 5%, 50pf external load parameter symbol min typ max units master clock frequency note) if crystal is not used. fmclk - 45 24.576 50 - 55 mhz % ac link interface timing bit_clk frequency bit_clk clock period(tbclk=1/fbclk) bit_clk low pulse width bit_clk high pulse width bit_clk rise time bit_clk fall time fbclk tbclk tclk_low tclk_high trise_clk tfall_clk - 36.0 36.0 - - 12.288 81.38 40.7 40.7 - - 45 45 6 6 mhz ns ns ns ns ns sync frequency sync low pulse width sync high pulse width sync rise time sync fall time tsync_low tsync_high trise_sync tfall_sync - - - - - 48 19.5 (240 cycle) 1.3 (16 cycle) - - - - - 6 6 khz m s (tbclk) m s (tbclk) ns ns setup time(sync, sdata_out) hold time(sync, sdata_out) sdata_in delay time from bit_clk rising edge sdata_in rise time sdata_in fall time sdata_out rise time sdata_out fall time tsetup thold tdelay trise_din tfall_din trise_dout tfall_dout 10.0 25.0 - - - - - - - - - - - - - 15 6 6 6 6 ns ns ns ns ns ns ns cold rest (sdata_out=l, sync=l) reset# active low pulse width reset# inactive to bit_clk delay trst_low trst2clk 1.0 162.8 (2 cycle) -- m s ns (tbclk) warm rest timing sync active low pulse width sync inactive to bit_clk delay tsync_high tsync2clk 1.0 162.8 (2 cycle) 1.3 (16 cycle) - m s (tbclk) ns (tbclk) ac-link low power mode timing end of slot 2 to bit_clk, sdata_in low ts2_pdwn - - 1.0 m s activate test mode timing setup to trailing edge of reset# hold from reset# rising edge rising edge of reset# to hi-z falling edge of reset# to ?l? tsetup2rst thold2rst toff tlow 15.0 100 - - - - - - - - 50 50 ns ns ns ns note ) the use of a crystal is recommended. if a master clock is supplied (or if an external oscillator is used), master clock should be supplied to xtal_in and xtal_out should be left open.
[asahi kasei] [AK4543] 1999/01 - 8 - n power on note that a AK4543 must be in cold reset at power on and reset# must be low until master clock becomes stable, or a reset must be done once master clock is stable. avdd or dvdd can be powered from independent supplies. bit_clk initialize registers start u p cr y stal oscillation sync=?l? sdata_out=?l? reset# vdd t rst2clk when using the AK4543 in the multiple codec mode, all codec?s connected to the ac-link are waken up at the same time. a common reset line should be used to insure clock synchronization after power up. n cold reset timing note that both sdata_out and sync must be low at the rising edge of reset# for a cold reset to occur. the AK4543 initializes all registers including the powerdown control registers, bit-clk is reactivated and each analog output is in hi-z state except for pc beep while reset# pin is low. the pc beep is directly routed to l & r line outputs when AK4543 is in cold reset. this is done to allow system sounds to be passed to speaker removing for an internal redundant speaker. at the rising edge of reset#, the AK4543 initiates the initialization of analog circuit , which takes 516fs cycles. after that, the mixer of the AK4543 is ready for normal operation. status bit in the slot 0 is ?0? (not ready) when the AK4543 is in reset period ( ?l?) or in initialization process. after initialization cycles, the status bit goes to ?1? indicating a ready condition. bit_clk v il reset# t rst2clk t rst_low sync=?l? sdata_out=?l? when the AK4543 is used under the multiple codec configuration and when cold reset is issued, all AK4543 connected to the ac-link will execute a cold reset concurrently. n warm reset the AK4543 initiates a warm reset process by receiving a single pulse on the sync(pin10). the AK4543 then clears pr4 bit and pr5 bit in the powerdown control register. however, warm reset does not influence pr0 ~ pr3 or pr6,7 bits in powerdown control register(26h). note that sync signal should synchronize with bit_clk after AK4543 starts to output bit_clk clock. and if an external clock is used, an external clock should be supplied before issuing a sync pulse for warm reset. v ih t sync2clk t sync_high bit_clk sync
[asahi kasei] [AK4543] 1999/01 - 9 - please refer to powerdown/powerup sequence of multiple codec configuration on the warm reset when the AK4543 is used under the multiple codec configuration .(see page 24, 25) n bit_clk timing t clk_low 50% t clk_high bit_clk n sync timing t sync_low v ih v il t sync_period t sync_high sync n setup and hold timing n signal rise and fall times (50pf external load : from 10% 90% of dvdd) t rise_clk bit_clk t fall_clk t rise_sync sync t fall_sync t rise_din sdata_in t fall_din t rise_dout sdata_out t fall_dout n ac-link low power mode timing slot 1 write to 0x26 bit_cl k sdata_in sdata_out t hold t s2_pdwn slot 2 data pr4=1 don?t care sdata_in sdata_out sync v oh t hold t setup v ol bit_clk v ih v il t delay v ih v il
[asahi kasei] [AK4543] 1999/01 - 10 - n activate test mode v ih v ih t setup2rst t off sdata_in bit_clk sdata_out hi-z reset# n akm test mode v ih v ih t setup2rst sync sdata_out=?l? reset# notes: 1 1. all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the rising edge of res et# causes the AK4543 ac-link outputs to go high impedance which is suitable for ate in circuit testing. note that the AK4543 enters in the ate test mode regardless sync is high or low. 2. bringing both sync high and sdata_out low for the rising edge of reset# causes akm test mode. 3. once test modes have been entered, the only way to return to the normal operating state is to issue cold reset which issues reset# with both sync and sdata_out low. 1 all the following sentences written with small italic font in this document quote the ac97 component specification.
[asahi kasei] [AK4543] 1999/01 - 11 - general description n ac ?97 connection to the digital ac ?97 controller 2 ac 97 communicates with its companion ac 97 controller via a digital serial link, ac-link. all digital audio streams, and command/status information are communicated over this point to point serial interconnect. a breakout of the signals connecting the two is shown in the following figure. sync ac?97 controller ac?97 bit_clk sdata_out sdata_in reset# n ac?97 digital interface the AK4543 incorporates a 5 pin digital serial interface that links it to the ac 97 controller. ac-link is a bi-directional, fixed rate(48khz), serial pcm digital stream. it handles multiple input, and output audio streams, as well as control register access es employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. dac and adc resolution of the AK4543 is 18 bit resolution. the data streams currently defined by the ac 97 specification include: l pcm playback 2 output slots 2 channel composite pcm output stream l pcm record data 2 input slots 2 channel composite pcm input stream l control 2 output slot control register write port l status 2 input slots control register read port sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on e ach rising edge of bit_clk. the receiver of ac-link data, the AK4543 for outgoing data and ac 97 controller for incoming data, samples ea ch serial bit on the falling edges of bit_clk. the AK4543 outputs bit_clk when it is assigned as primary codec by the codec id configuration id1# and id0#. the other hand, t he AK4543 receives bit_clk when assigned as the secondary codec from the primary device. the ac-link protocol provides for a special 16-bit slot (slot 0) wherein each bit conveys a valid tag for its corresponding tim e slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the c urrent audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (the AK4543 for the input stream, ac 97 controller for the output stream), to stuff all bit positions with 0s du ring that slots active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame wher e sync is high is defined as the tag phase. the remainder of the audio frame where sync is low is defined as the data phase. note that sdata_out and sdata_in data is delayed one bit_clk because ac?97 controller causes sync signal high at a rising edge of bit_ clk which initiates a frame. ?output? stream means the direction from ac ?97 controller to the AK4543, and ?input? stream means the direction from the AK4543 to ac?97 controller 2 all the following sentences written with small italic font in this document quote the ac97 component specification.
[asahi kasei] [AK4543] 1999/01 - 12 - pcm(dac) right all ?0? all ?0? 12 11 10 9 8 7 6 5 4 3 2 1 48khz data phase tag phase slot 0 sync all ?0? all ?0? all ?0? all ?0? all ?0? all ?0? all ?0? pcm(dac) right pcm(dac) left command data command address tag all ?0? all ?0? all ?0? all ?0? all ?0? all ?0? all ?0? all ?0? pcm(adc) right pcm(adc) left status data status address sdata in tag all ?0? all ?0? all ?0? all ?0? pcm(dac) right pcm(dac) left all ?0? all ?0? all ?0? command data command address sdata out tag all ?0? all ?0? all ?0? all ?0? all ?0? pcm(dac) left all ?0? all ?0? command data command address tag all ?0? codec id1:codec id0=0:0 or 0:1 codec id1:codec id0=1:0 codec id1:codec id0=1:1 ac-link protocol identifies 13slots of data per frame. the frequency of sync is fixed to 48khz. only slot 0, which is the tag phase, is 16bits, all other slots are 20bits in length. these slots are explained in later sections. ac-link audio output frame (sdata_out) a) slot 0 ?1/0? ?1/0? slot6 slot5 slot4 slot3 slot2 slot1 valid frame ?1/0? sync slot 1 slot 0 1 bit_clk dela y sdata_out bit_clk ?1/0? ?1/0? ?0? ?0? slot10 ?0? ?0? ?0? slot9 slot8 slot7 slot11 slot12 ?0? ?0? ?0? ?0? ?0? ?0? bit15 bit14 bit13 bit12 bit11 bit10 bit9? bit8 bit7? bit6? bit5? bit4 bit3 bit2 bit1 bit0 primary codec (codec id1: codec id0 = 0 : 0) ?0? ?0? slot6 slot5 slot4 slot3 slot2 slot1 valid frame ?1/0? sync slot 1 slot 0 1 bit_clk dela y sdata_out bit_clk ?1/0? ?1/0? ?1/0? ?0? slot10 ?1/0? ?0? ?0? slot9 slot8 slot7 slot11 slot12 ?1/0? ?1/0? ?1/0? ?0? ?0? ?1/0? bit15 bit14 bit13 bit12 bit11 bit10 bit9? bit8 bit7? bit6? bit5? bit4 bit3 bit2 bit1 bit0 secondary codec (codec id1 : codec id0 = 0 : 1 or 1 : 0 or 1 :1 ) the AK4543 checks bit15 (valid frame bit). note that when the valid frame bit is ?1?, at least one bit14-6 ( slot 1- 9) or bit1-0 must be valid, bit5-2 will be ?0?and should be ignored. if bit15 is ?0?, the AK4543 ignores all following information in the frame. the AK4543 then checks the validity of each bit in the tag phase (slot 0). if each bit is ?0?, the AK4543 ignores the slot indicated by ?0?. on the other hand, if each bit is ?1?, the slot is valid. all bits in slot10-12(bit5-3) are ?0? and bit2 is also ?0?. the AK4543 monitors bit1 and 0, which are codec id configuration bits used in multiple codec implementations. these bits are used to identify which codec the frame data is issued to.
[asahi kasei] [AK4543] 1999/01 - 13 - when codec id configuration bits1 and 0 which are set by the codec id configuration 45/46 strapping pins(codec id0# and id1#) are set to zero(00), the frame is aimed for the primary codec. and when codec id configuration bit1 and 0 are set to non-zero values(01, 10, or 11), the frame is meant for secondary codec. a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on th e immediately following falling edge of bit_clk, the AK4543 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac 97 controller transit ions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising ed ge of bit_clk, and subsequently sampled by the AK4543 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. data should be sent to the ac?97 codec with msb first through the pin labled sdata_out. the following table shows the relationship of bits14&13 and the read/write operation s depending on codec id configuration. bit 15 valid frame bit 14: slot1 valid bit (command address) bit 13: slot 2 valid bit (command data) read/write operation of primary AK4543 read/wirte operation of secondary AK4543 1 1 1 read/write(normal operation) ignore 1 0 1 ignore ignore 1 1 0 read: normal operation write: ignore ignore 1 0 0 ignore read/write(normal operation) AK4543 addressing: slot0 tag bits b) slot1:command address port slot1 gives the address of the command data, which is given in the slot 2. the AK4543 has 20 valid registers of 16bit data. see page17(see ac?97 register map). bit15 ?1/0? ?1/0? bit14 bit16 bit17 bit18 bit19 ?1/0? command address port slot 2 slot 0 slot 1 sdata_out bit_clk ?1/0? ?1/0? ?0? ?0? ?0? ?0? bit9 bit9 bit10 bit12 bit11 bit13 ?1/0? ?1/0? ?1/0? ?0? bit2 ?0? ?0? bit16 bit0 bit1 bit17 bit18 bit19 bit 19: read/write command 1=read, 0=write bit 18:12 control register index (see ?ac?97 register map? for the detail) bit 11:0 reserved (?0?) bit18 is equivalent to the most significant bit of the index register address. the AK4543 ignores from bit11 to bit0. these bits will be reserved for future enhancement and must be stuffed with 0?s by the ac?97 controller. c)slot2:command data port bit12 bit15 ?1/0? ?1/0? bit14 bit16 bit17 bit18 bit19 ?1/0? command data port slot 3 slot 1 slot 2 sdata_out bit_clk ?1/0? ?1/0? ?0? bit3 bit4 bit5 bit6 bit13 ?1/0? ?1/0? ?1/0? ?1/0? ?1/0? ?0? bit2 ?0? ?0? bit16 bit0 bit1 bit17 bit18 bit19 bit19:4 control register write data (if bit 19 of slot 1 is ?1?, all bit19:4 should be ?0?) bit3:0 reserved(?0?) if bit19 in slot1 is ?0?, a write command, the ac?97 controller must output command data port data in slot 2 of the same frame . if the bit19 in slot1 is ?1?, a read, the AK4543 will ignore any command data port data in slot2. bit19 is equivalent to d15 bit of mixer register value.
[asahi kasei] [AK4543] 1999/01 - 14 - d)slot3 pcm playback left channel (18bits) in the case of codec id1:codec id0=0:0 or 0:1, the AK4543 uses the playback(dac) data format in slot3 for left channel. playback data format is 18bits msb first 2?s complement. the ac?97 controller should stuff bits1-0 with ?0?. if valid bit (slot3) in the slot 0 is invalid (?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? e)slot4 pcm playback right channel (18bits) in the case of codec id1:codec id0=0:0 or 0:1, the AK4543 uses the playback(dac) data format in the slot4 for right channel. playback data format is msb first. data format is 18bits 2?s complement. the ac?97 controller should stuff bits1-0 with ?0?. if valid bit (slot 4) in the slot 0 is invalid ( ?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? f)slot5 is not used in the AK4543 the AK4543 will ignore stuffed in this slot. g)slot6 pcm playback left channel (18bits) in case of codec id1:codec id0=1:1, the AK4543 uses the playback(dac) data in slot 6 for left channel. playback data format is 18bits msb first 2?s complement. the ac?97 controller should stuff bit1-0 with ?0?. if valid bit (slot6) in the slot 0 is invalid ( ?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? h)slot7 pcm playback left channel (18bits) in case of codec id1:codec id0=1:0, the AK4543 uses the playback(dac) data in slot7 for left channel. playback data format is 18bits msb first 2?s complement. the ac?97 controller should stuff bit1-0 with ?0?. if valid bit (slot7) in the slot 0 is invalid ( ?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? i)slot8 pcm playback right channel (18bits) in case of codec id1:codec id0=1:0, the AK4543 uses the playback(dac) data in slot8 for right channel. playback data format is 18bits msb first 2?s complement. the ac?97 controller should stuff bit1-0 with ?0?. if valid bit (slot8) in the slot 0 is invalid ( ?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? j)slot9 pcm playback right channel (18bits) in case of codec id1:codec id0=1:1, the AK4543 uses the playback(dac) data in slot 9 for right channel. playback data format is 18bits msb first 2?s complement. the ac?97 controller should stuff bit1-0 with ?0?. if valid bit (slot9) in the slot 0 is invalid ( ?0?), the AK4543 interprets the data as all ?0?. bit19:2 playback data bit 1:0 ?0? k)slot10-12 is not used in the AK4543 the AK4543 will ignore stuffed in these data slots.
[asahi kasei] [AK4543] 1999/01 - 15 - n ac-link input frame(sdata_in) each ac-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control. a) slot0 slot0 is a special frame, and consists of 16bit s. slot0 is also called the ?tag phase?. the AK4543 supports bits 15-11 and bits1-0. each bit indicates ?1?=valid(normal operation) or ready, ?0?=invalid(abnormal operation) or not ready. if the first bit in the slot 0 is valid, the AK4543 is ready for normal operation. 3 if the ?codec ready? bit is invalid, the following bits and remaining slots are all ?0?. the ac?97 controller should ignore the following bits in the slot 0 and all other slots. bit 14 means that slot 1(status address) output is valid or invalid. and bit 13 means that slot 2(status data ) is valid or invalid. the following table shows the relationship between bit 14,13 and each status of the AK4543. bit 15 (codec ready) bit 14 (status address) bit 13 (status data) status 1 1 1 there is a read command in the previous frame. then both slot 1 and slot 2 output normal data. if the access to non-implemented register or odd register is requested, the AK4543 returns ?valid 7-bit register address in slot 1 and returns ?valid?0000h data in slot 2 on the next ac-link frame. 1 1 0 prohibited or non-existing 1 0 0 there is no read command in the previous frame. both slot 1 and slot 2 output all?0?. 1 0 1 prohibited or non-existing note 1). the above read sequence is done as response for previous frames read command. that is, if the previous frame is a write command, AK4543 outputs bit1 4 =?0?, bit13 =?0? and slot 1&2 = all?0?. bit12 means the output of slot 3( pcm(adc) left) is valid or invalid. and bit 11 means the output of slot 4(pcm(adc)left) is valid or invalid. bits10-0 are filled with ?0?. a new audio input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the AK4543 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the AK4543 transitions sdata_ in into the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of bi t_clk, and subsequently sampled by the ac 97 controller on the following falling edge of bit_clk. this sequence ensures that data transit ions, and subsequent sample points for both incoming and outgoing data streams are time aligned. ?0? bit4 ?1/0? ?1/0? slot6 slot7 slot5 slot4 slot3 slot2 slot1 codec ready ?1/0? sync slot 1 slot 0 sdata_in bit_clk ?1/0? ?1/0? ?0? ?0? ?0? slot12 ?0? ?0? ?0? ?0? bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit3 bit2 bit1 bit0 slot8 slot11 ?0? bit7 b) slot1 status address port audio input frame slot1s stream echoes the control register index, for historical reference, for the data to be returned in sl ot2. (assuming that slots1 valid bit and slot2 valid bit in the slot0 had been tagged valid by the AK4543) bit15 ?1/0? ?1/0? bit14 bit16 bit17 bit18 bit19 status address port slot 2 slot 0 slot 1 sdata_in bit_clk ?1/0? ?1/0? ?0? ?0? ?0? ?0? ?0? bit9 bit9 bit10 bit12 bit11 bit13 ?1/0? ?1/0? ?1/0? ?0? bit2 ?0? ?0? bit16 bit0 bit1 bit17 bit18 bit19 3 when the ac97 is not ready for normal operation, output bits are not specified in this documents and should be considered as invalid.
[asahi kasei] [AK4543] 1999/01 - 16 - this address shows the register index for which data is being returned in the slot2. this address port is a copy of slot1 of the output frame, and index address input to sdata_out is loop ed back to the ac?97 controller through sdata_in. this allows the controller to insure the AK4543 receives the correct data. c)slot2: status data port status data addressed by the command address port of output stream is output through sdata_in pin. bit19:4 control register read data (the contents of indexed address in the slot 1) bit3:0 ?0? note that the address of status data port data is consistent with status address port data of slot 1 in the same frame . if the read operation is issued in the frame n by the ac?97 controller, status data port data is output through sdata_in in the frame n+1. note that data is only available in this frame, only one time and that the following frames are invalid if another read operation is not issued. d)slot3: pcm record left channel record(adc) data format is 18bits msb first 2?s complement. lower 2bits of the frame are ignored. if adc block is powered down, slot-3 valid bit in the slot 0 is invalid ( ?0?), and data is as all ?0?. bit19:2 audio adc left channel output bit1:0 ?0? e)slot4: pcm record right channel record(adc) data format is 18bits msb first 2?s complement. lower 2bits of the frame are ignored. if adc block is powered down, slot-4 valid bit in the slot 0 is invalid ( ?0?), and data is as all ?0?. bit19:2 audio adc right channel output bit1:0 ?0? f)slot5: modem line codec the AK4543 does not incorporate the modem codec, all bits are stuffed with ?0? in this slot. bit19:0 ?0? g)slot6: microphone record data the AK4543 does not incorporate the 3 rd adc for microphone, all bits are stuffed with ?0? in this slot. bit19:0 ?0? h)slots7-12 reserved for future enhancement bits19:0 ?0?
[asahi kasei] [AK4543] 1999/01 - 17 - n ac?97 register map each register is a 16bit word. note: the AK4543 outputs ?valid? 0000h if the controller reads an unused or invalid register address . reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 ? 0 ?? 1 ?? 0 ?? 1 ?? 1 ?? 0 ?? 1 ?? 0 ?? 1 ?? 0 ?? 1 ?? 0 ?? 0 ?? 0 ?? 0 ? 2d50h 02h master volume mute x ml5 ml4 ml3 ml2 ml1 ml 0 xx mr5 mr4 mr3 mr2 mr1 mr0 8000h 04 linvl volume mute x ml5 ml4 ml3 ml2 ml1 ml 0 xx mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mute xxxxxxxxx mr5 mr4 mr3 mr2 mr1 mr0 8000h 0ah pc_beep volume mute x x x x x x x x x x pv3 pv2 pv1 pv0 x 0000h 0ch phone volume mute x x x x x x x x x x gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute xxxxxxxx 20db x gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ah record select x x x x x sl2 sl1 sl0 x x x x x sr2 sr1 sr0 0000h 1ch record gain mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000h 20h general purpose pop x 3d x x x mix ms lpbk x x x x x x x 0000h 22h 3d control x x x x x x x x x x x x x x dp1 dp0 0000h 26h powerdown ctrl/stat pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc na 28h extended audio id id1 id0 x x x x amap x x x x x x x x x x200h 7ch vendor id1 ? 0 ?? 1 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 1 ?? 0 ?? 1 ?? 0 ?? 0 ?? 1 ?? 0 ?? 1 ?? 1 ? 414bh 7eh vendor id2 ? 0 ?? 1 ?? 0 ?? 0 ?? 1 ?? 1 ?? 0 ?? 1 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 1 ?? 0 ? 4d02h *) vender id of akm is ?akm? :this id has been approved by intel. *) the AK4543 outputs ?x? bits as ?0?. *) a write on ?invalid? registers will not affect the operation of the AK4543. *) anl, dac, adc bit in register 26h are all ?0? following cold reset. when each section is ready for normal operation, the coresponding bit becomes ?1?. the powerdown register(26h) is not affected by a write to reset register(0h). see ?mixer registers? in ac?97 specification for details. vref is controlled only by pr3. n reset register (index 00h) when any value is written to this register , all registers in the AK4543 except for register ?26h? powerdown ctrl/stat register are reset to the default values. the value of this register is not altered. reading this register returns ?2d50h?composed of the id code of the part, a code for the type of 3d enhancement, 18 bit adc/dac resolution, and a code for true line level out. *setting d14 ? d10 ?01011? means akm 3d enhancement which is registered in audio codec ?97 component specification rev 1.03 and 2.1 . *setting d8 ?1? indicates 18bit adc resolution and d6 ?1? does dac resolution. *setting d4 ?1? means true line level out is supported with volume control(index 04h). n play master volume registers (index 02h ,06h) and linvl(true line level out) volume register(index 04h) the following table shows the relationship between bits and the attenuation value with step size of 1.5db. the AK4543 has a range of 0db to ?46.5db. the AK4543 does not support the optional mx5 bit. the AK4543 detect s when mx5 is set and set all 5 lsbs to 1s. example: when t he driver writes a 0 1xxxxx the AK4543 interpret that as 0011111. when this register is read, the returned value is 0011111. mute mx5 mx4 mx3 mx2 mx1 mx0 att. 0000000 0db 0000001 -1.5db 0000010 -3.0db 0000011 -4.5db ------------------------------------------------------------------------- 0011110 -45.0db 0011111 -46.5db ------------------------------------------------------------------------- 0 1 xxxxx -46.5db ------------------------------------------------------------------------- 1xxxxxx mute
[asahi kasei] [AK4543] 1999/01 - 18 - n pc beep register (index 0ah) the following table shows the relationship between bits and the attenuation value. the attenuation step is -3db with a range of 0 to ?45db. pc_beep of the AK4543 is mute off at default state. the pc beep is routed to l & r line outputs directly when AK4543 is in a reset state(reset# is l). this is so that power on self test(post) codes can be heard by the user in case of a hardware problem with the pc. after reset# goes h, direct pc beep pass thru becomes off. mute pv3 pv2 pv1 pv0 att. 00000 0db 00001-3.0db 0 0 0 1 0 -6.0db -------------------------------------------------------------- 01111-45.0db 1 x x x x mute n analog mixer input gain registers (index 0ch-18h) the following table shows the relationship between bits and the gain/attenuation value. attenuation step is 1.5db with a range of +12db to ?34.5db. mute gx4 gx3 gx2 gx1 gx0 att. 000000 +12db 000001 +10.5db ----------------------------------------------------------------------- 001000 0db 001001 -1.5db ----------------------------------------------------------------------- 011110 -33.0db 011111 -34.5db 1xxxxx mute n record select control register (index 1ah) sr2 sr1 sr0 att. 0 0 0 mic 0 0 1 cd in (r) 0 1 0 video in (r) 0 1 1 aux in (r) 1 0 0 line in (r) 1 0 1 stereo mix (r) 1 1 0 mono mix 1 1 1 phone sr2 sl1 sl0 att. 0 0 0 mic 0 0 1 cd in (l) 0 1 0 video in (l) 0 1 1 aux in (l) 1 0 0 line in (l) 1 0 1 stereo mix (l) 1 1 0 mono mix 1 1 1 phone
[asahi kasei] [AK4543] 1999/01 - 19 - n record gain register (index 1ch) mute gx3 gx2 gx1 gx0 gain 00000 0db 0 0 0 0 1 1.5db 0 0 0 1 0 3.0db -------------------------------------------------------------- 0 1 1 1 1 22.5db 1 x x x x mute n general purpose register (index 20h) the following table indicates how to control several miscellaneous functions of the AK4543. bit function pop d15 pcm(dac) bypass 3d 0= via 3d path, 1= 3d bypass 3d d13 3d stereo enhancement 0=off, 1=on mix d9 mono output select 0=mix, 1=mic ms d8 mic select 0=mic1, 1 =mic2 lpbk d7 adc/dac loopback mode 1= loopback an active bit(?1?) in d15(pop) will pass dac output to line_out or lnlvl_out directly, while a ?0? in d15 will put dac output into input mixers or akm?s 3d enhancement circuit. d13(3d) will activate the akm?s 3d enhancement. lpbk(adc/dac loopback mode) bit enables loopback of the adc output to slot3 &4 of dac input for both the primary codec and secondary codec on the same ac-link . generally done for system testing. n 3d control register (index 22h) the following table shows the relationship between the bit and depth of 3d enhancement. dp1 dp0 depth recommended application 0 0 0% off 0 1 50% audio 1 0 70% audio 1 1 100% game
[asahi kasei] [AK4543] 1999/01 - 20 - n powerdown control/status register (index 26h ) bitsd0 to d3 are read only status bits. any write to these bits will not affect the operation of the AK4543. these bits are used as status bits to subsections of the ac ?97 codec. a ?1? indicates the subsection of the AK4543 is ?ready? or that is capable of performing in normal operation. bit function ref d3 vref up to nominal state 0=not ready, 1=ready, anl d2 analog mixers, etc ready 0=not ready, 1=ready dac d1 dac section ready to accept data 0=not ready, 1=ready adc d0 adc section ready to transmit data 0=not ready, 1=ready the power down modes are as follows. bit function pr0 d8 pcm in adc?s & input mux powerdown pr1 d9 pcm out dacs powerdown pr2 d10 analog mixer powerdown (vref still on) pr3 d11 analog mixer powerdown (vref off) pr4 d12 digital interface (ac-link) powerdown pr5 d13 internal clk disable pr6 pr7 d14 d15 true line level out powerdown eapd(external amplifier powerdown) when pr3 is set to ?1?, the adc, dac, mixer, true line level out, and vref are powered down even if any prx bit are ?0?. when pr3 bit is reset to ?0?, the AK4543 resumes the previous state by referencing previous prx bit. in this case, the AK4543 outputs corresponding slot-x valid bits in the slot 0 as ?0? until the AK4543 results in normal operation(codec ready) . eapd(external amplifier power down) bit controls an external audio amplifier. eapd=?0? places a ?0?(l) on the output pin, enabling an external audio amplifier, eapd= ?1?(h) shuts it down. powered up default is eapd=?0?(external audio amplifier enabled). n extended audio id(index 28h) the extended audio id(28h) is a read only register. 2bits d15&d14 can be read for codec identification. d15 ,14 are automatically set with the codec id1#(46pin) and id0#(45pin). id1# and id0# can be strapped and adopt inverted polarity and default to 00= primary(via internal pull up) when left floating. depended on codec id configuration, the AK4543 is assigned to primary codec or secondary codec. note that codec id configuration has to be fixed before powering up of the device. id1#(pin 46) id0#(pin45) physical connection logic value physical connection logic value configuration (codec id) nc 0 nc 0 primary id00 nc 0 gnd 1 secondary id01 gnd 1 nc 0 secondary id10 gnd 1 gnd 1 secondary id11 the amap (bit d9 of this read only register) will always be set to ?1? indicating that dac input slot will follow to ac?97 recommendation as shown in next table.(codec id is configured via id1#m id0# pins) the audio dac mapping can be changed based on the codec id configuration. ac-link frame data used for dacs codec id pcm left dac uses data from slot# pcm right dac uses data from slot# comments expected use 00 3 4 original definition(master) 01 3 4 original definition(docking) 10 7 8 left/right surround channels 11 6 9 center/lfe channels
[asahi kasei] [AK4543] 1999/01 - 21 - n vendor id registers (index 7ch , 7eh) this register is a read only register that is used to determine the specific vendor identification. the id method is microsoft plug and play vendor id code with upper byte of 7ch register, the first character of that id, lower byte of 7ch register, the second cha racter and upper byte of 7eh register the third character. these three characters are ascii encoded. lower byte of 7e register is for the vendor revision number. akm?s vender id is ?akm?, and revision number is 02. as ascii code ?a? is 41h, ?k? is 4bh, and ?m? is 4dh, vendor id registers are 414bh and 4d0 2h respectively.
[asahi kasei] [AK4543] 1999/01 - 22 - pd 26[10] avss1 avss2 test2 eapd xtl_in mute(0c[15]) mute(0e[15]) mute(10[15]) mute(0a[15]) gain (16[4:0]) gain (16[12:8]) gain (14[4:0]) gain (14[12:8]) gain ( 12 [ 4:0 ]) gain ( 12 [ 12:8 ]) gain ( 10 [ 4:0 ]) gain(10[12:8]) gain (0c[5:0]) pc_vol (0a[4:1]) mux (20[8]) (0e[6]) gain (0e[5:0]) phone mono_out line_out_r line_ out_l pc_beep line_in_r line_in_ cd_r cd_l video_r video_l aux_r aux_l mic2 mic1 pd 26[8] pd 26[8] 1a[10:8] mux mixer ? (l) ? (r) ? (l) ? (r) volta g e reference ? mono volume 06[5:0] gain 1c[3:0] gain 1c[11:8] adc.l dac.l dac.r adc.r sync bit_clk sdata_out sdata_in dvss1 reset# dvdd1 xtl_out AK4543 vref afilt2 afilt1 mixer registers ac97 digital interface mixer mixer mixer mux 20[9] mux 20db mute(16[15]) mute(16[15]) mute(14[15]) mute(14[15]) mute ( 12 [ 15 ]) mute ( 12 [ 15 ]) mute ( 10 [ 15 ]) mute(18[15]) gain (18[12:8]) mute(18[15]) gain (18[4:0]) master volume 02[5:0] master volume 02[13:8] mute 06[15] mute 02[15] mute 02[15] mute 1c[15] mute 1c[15] 1a[2:0] pd 26[9] pd 26[10] pd 26[10] pd 26[10] pd 26[10] pd 26[16] pd 26[11] 20[7] 20[7] pd 26 [ 8 ] 1/2 vradda 1/2 ? mixer dvss2 dvdd2 3dcap mux pop 20[15] mux mux 3d 20[13] 3d 20[13] lnlvd volume 04[13:8] mute 04[15] lnlvl volume 04[5:0] mute 04[15] lnlvl_out_r lnlvl_out_l pd 26[13] pd 26[13] reset# reset# pd 26[14] cd_gnd AK4543 block diagram avdd2 test3 avdd1 codec id0# codec id1# ? ? mixer mixer 3d 22[1:0] sel_cmos mux 1/2
[asahi kasei] [AK4543] 1999/01 - 23 - n power management/low power modes the AK4543 is capable of operating at multiple reduced power modes for when no activity is required. the state of power down is controlled by the powerdown register (26h). there are 8 separate commands for power down. see the table below for the different modes. as the AK4543 operates at static mode, the registers will not lose their values even if the master clock is stopped only upon power. powerdown mode truth table adc dac mixer vref aclink internal clk lnlvl_out eapd pr0=1 pd dont care dont care dont care dont care dont care dont care dont care pr1=1 dont care pd dont care dont care dont care dont care dont care dont care pr2=1 dont care dont care (no dac out) pd dont care dont care dont care pd dont care pr3=1 pd pd pd pd dont care dont care pd dont care pr4=1 pd pd dont care dont care pd dont care dont care dont care pr5=1 pd pd dont care dont care pd pd dont care dont care pr6=1 dont care dont care dont care dont care dont care dont care pd dont care pr7=1 dont care dont care dont care dont care dont care dont care dont care pd *: pd means powerdown . *: no dac out means that there is no pcm out because mixer is disabled. from normal operation sequential writes to the powerdown register are performed to power down subsections of the AK4543 one at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac 97 digital interface (a c-link). the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac 97 controller will s end a pulse on the sync line issuing a warm reset. this will restart the AK4543 digital (resetting pr4 to zero). the AK4543 can also be woken up with a cold reset. a cold reset will cause a loss of values of the registers as a cold reset will set them to their default sta tes. when a subsection is powered back on the powerdown control/status register (index 26h) should be read to verify that the section is re ady (i.e. stable) before attempting any operation that requires its normal operation. and the below figure illustrates one example of procedure to do a complete powerdown/power up of AK4543. normal adcs off pr0 dacs off pr1 digital i/f off pr4 pr0=1 pr1=1 pr2=1 shut off ac-link w arm reset pr1=0 & dac=1 pr0=0 & adc=1 analog off pr2 or pr3 pr4=1 pr2=0 & anl=1 default cold reset ready = 1 one example of AK4543 powerdown/powerup flow when pr3 bit is set to ?1?, the adc, dac, mixer, true line level out, and vref will be powered down even if any prx bits are ?0?. when pr3 bit is reset to ?0?, the AK4543 resumes with the previous state by referencing prx bit. in this case, the AK4543 outputs ?0? (invalid) for corresponding slot-x valid bits in the slot 0 until the corresponding block of the AK4543 is operating with normal operation. setting the pr4 bit causes the powerdown mode of AK4543 and ac-link of AK4543 shut down. in this case, when warm reset is executed, pr4 bit is cleared and the ac-link is reactivated. a cold reset is issued , the AK4543 is restored to operation with the default register settings. in addition, setting pr5 bit causes the powerdown mode of AK4543 and the internal clock of AK4543 to be stopped. when a warm reset is done in this case, pr5 bit is cleared to 0 and internal clock and ac-link are reactivated. when cold reset is executed, AK4543 is set up to the operation with default register setting, no powerdown modes active.
[asahi kasei] [AK4543] 1999/01 - 24 - the next figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this is used when the user is playing a cd (or external line_in source) through the ac ?97 codec to the speakers but has most of the system in a low power mode. the procedure for this follows the previous except that the analog mixer is never shut down. normal adcs off pr0 dacs off pr1 digital i/f off pr4 pr0=1 pr1=1 pr4=1 shut off ac-link w arm reset pr1=0 & dac=1 pr0=0 & adc=1 AK4543 powerdown/powerup flow with analog still alive n powerdown/powerup sequence of multiple codec configuration there can be up to 4 codecs on the extended ac-link. multiple codec ac-link implementations must run off a common bit_clk. the primary codec generates the master ac-link bit_clk for both the ac ?97 digital controller and any secondary codecs. the AK4543 may be used as a master or slave in any systems using more than one codec. sync bit_clk sdata_out reset# sdata_in0 sdata_in1 sdata_in2 sdata_in3 sync bit_clk sdata_out reset# sdata_in digital controller ac 97 ac 97 or mc 97 optional 4th ac 97 sync bit_clk sdata_out reset# sdata_in sync bit_clk sdata_out reset# sdata_in multiple codec example under the multiple codec circumstances, there is no restriction on setting pr0(adc), pr1(dac), pr2(mixer), pr6(lnlvl_out) and pr7(eapd) to ?1? or ?0?. as suggested in the ac?97 specification rev2.1, the ac-link powerdown(pr?4?) and vref powerdown(pr5=?1?) under the multiple codec configuration are not recommended in order to continue supplying bit_clk to the secondary codecs.
[asahi kasei] [AK4543] 1999/01 - 25 - the below table shows the relationship for the ac-link powerdown/powerup procedure. ac-link powerdown procedure subsequent procedure for powerup comments reset#=l cold reset cold reset wakes up all of codecs with default register setting concurrently. shutdown(complete powerdown) cold reset cold reset wakes up all of codecs with default register setting concurrently. note: 1) the ac-link powerdown of primary ac?97 will stop supplying the bit_clk to the secondary ac ?97. 2) when the ac-link powerdown is issued to the secondary of ac ?97, the secondary of ac?97 will go to the ac- link powerdown and warm reset will be followed by syn signal at the next time frame. n testability activating the test modes ac 97 has two test modes. one is for ate in circuit test and the other is for vendor specific tests. ac 97 enters the ate in circuit test mode regardless of sync signal (high or low) if sdata_out is sampled high at the trailing edge of reset#. if ac 97 enters akm test mode when coming out of reset if sync is high with sdata_out low. these cases will never occur during standard operating conditions. regardless of the test mode, the ac 97 controller must issue a cold reset to resume normal operation of the ac 97 codec. test mode functions ate in circuit test mode when ac 97 is placed in the ate test mode, its digital ac-link outputs (i.e. bit_clk and sdata_in) are driven to a high impedance state. this allows ate in circuit testing of the ac 97 controller.
[asahi kasei] [AK4543] 1999/01 - 26 - system design the following figure shows the system connection diagram. primary codec: codec id1:codecid0=0:0 avdd: 5v dvdd: 3.3v or 5v 3.3v : 48pin open 5.0v : 48pin dgnd
[asahi kasei] [AK4543] 1999/01 - 27 - secondary codec codec id1:codecid0=0:1,1:0 or 1:1 this figure is the case of id1 =0 and id0=1. avdd: 5v dvdd: 3.3v or 5v 3.3v : 48pin open 5.0v : 48pin dgnd
[asahi kasei] [AK4543] 1999/01 - 28 - 1. grounding and power supply decoupling avdd1 and avdd2 should be connected and derived from same avdd. and dvdd1 and dvdd2 also should be connected and derived from same dvdd. analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4543 as possible, with the small value ceramic capacitor being the nearest.the most important capacitor placements are on the vref pin and avdd pins. no specific power supply sequencing is required on the AK4543. 2. on-chip voltage reference the on-chip voltage reference is output on the vradda, vref pins are used for decoupling. a electrolytic capacitor less than 10uf in parallel with a 0.1 uf ceramic capacitor attached to these pins eliminates the effects of high frequency noise. no load current may be drawn from vradda, or vref pins. all signals, especially clocks, should be kept away from the vradda, and vref pins in order to avoid unwanted coupling into delta-sigma modulators. 3. codec id configuration pin 45,46 id1#(pin 46) id0#(pin45) physical connection logic value physical connection logic value configuration nc 0 nc 0 primary nc 0 gnd 1 secondary id01 gnd 1 nc 0 secondary id10 gnd 1 gnd 1 secondary id11 4.anlog input since many analog levels can be as high as 2vrms, the circuit shown below can be used to attenuate the analog input 2vrms to 1vrms which is the maximum voltage allowed for all the stereo line-level inputs. j15 line_in_l j4 line_in_r 5.sel_cmos#(48pin) when dvdd is 3.3v for support of cmos level, pin 48 must be open. pin 48 must be dgnd as the below figure in the case of dvdd is 5.0v for ttl level this sel_coms# has to be fixed before powering up the AK4543. 6.pc_beep if pc_beep isn?t used, this input pin should be nc(open) or connected to analog-ground via capacitor. in this case, the register for pc- beep(04h,d15) should be set to mute on ?1?. (note that the default of pc_beep is mute off.) in addition, when pc_beep is connected through capacity to analog-ground, pc_beep is recommended to be separated from other non-used input pins.
[asahi kasei] [AK4543] 1999/01 - 29 - package 9.0 + 0.2 0.19 + 0.05 0.17 + 0.05 9.0 + 0.2 1 12 13 24 25 36 37 48 0.10 0.5 1.7 m ax 010 0.5 + 0.2 7.0 7.0 0.10 + 0.07 1.4ty p 0.01 m 48p i n lqfp(un i t :m m)
[asahi kasei] [AK4543] 1999/01 - 30 - marking 1 AK4543vq xxxxxxx japan 1) pin #1 indication 2) date code : xxxxxxx (7 digits) 3) marketing code : AK4543vq 4) country of origin 5) asahi kasei logo
[asahi kasei] [AK4543] 1999/01 - 31 - appendix 1. summary of the relationship of slot 0 tag bit between sdata_out and sdata_in whenever the ac ?97 digital controller addresses the primary AK4543 or the AK4543 responds to a read command, slot 0 tag bits should always be set to indicate actual slot 1 and slot 2 data validity. function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1-0 (codec id) ac ?97 digital controller primary read frame n, sdata_out 11000 ac ?97 digital controller primary write frame n, sdata_out 11100 AK4543 status frame n+1, sdata_in 11100 primary AK4543 addressing: slot 0 tag bits when the ac ?97 digital controller addresses a secondary AK4543, the slot 0 tag bits for address and data must be ?0?. a non-zero 2-bit codec id in the lsbs of slot 0 indicates a valid read or write address in slot 1, and the slot 1 r/w bit indicates presence or absence of valid data in slot 2. function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1-0 (codec id) ac ?97 digital controller secondary read frame n, sdata_out 1 0 0 01, 10, or 11 ac ?97 digital controller secondary write frame n, sdata_out 1 0 0 01, 10, or 11 AK4543 status frame n+1, sdata_in 11100 secondary AK4543 addressing: slot 0 tag bits important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b)a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
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